LegLite Simulated CPU

For this project, the goal was to simulate a computer CPU capable of processing instructions formatted in a simplified LEGv8 instruction set. To do this, we used SystemVerilog to design various components such as an ALU, registers, and multiplexers and organize them in such a way that allows instructions to be interpreted.

Of the team, I was responsible for organizing and linking together the coded components. This would be like wiring the components together on a physical board.

Below is an example of a written module: the 4-1 MUX. This would take in 4 inputs and determine which one to push to the output.

---

// 4:1 Multiplexer
module MUX4(
	result,  // 16 bit output
	indata0, // Input 0
	indata1, // Input 1
	indata2, // Input 2
	indata3, // Input 3
	select   // 2-bit select input
	);	

output [15:0] result;
input [15:0] indata0, indata1, indata2, indata3;
input [1:0] select;

reg [15:0] result;

always @(indata0 or indata1 or indata2 or indata3 or select)
	case(select)
	0: result = indata0;
	1: result = indata1;
	2: result = indata2;
	3: result = indata3;
	endcase

endmodule

---

With this project, my biggest takeaway was how to follow complex instructions. Since each individual part of the CPU had to be programmed separately, each had to be made in such a way that follows the instructions very closely or else the whole thing may not work in the end. Looking back, this is similar to how programming is done in the workspace where you’re given a spec sheet and are tasked with coding the solution.